FAULT-TOLERANT ADAPTIVE XY ROUTING FOR MULTIPROCESSORS IN HPC NETWORK

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Volume 3 (1), June 2020, Pages 94-118

Pankaj Dadheech, Ankit Kumar

Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur, Rajasthan, India, This email address is being protected from spambots. You need JavaScript enabled to view it., This email address is being protected from spambots. You need JavaScript enabled to view it.

Abstract

Interconnection of networks use in multiprocessors multi-computer and distributed shared memory architecture; basically, it connects many networks simultaneously in each time interval. The objective of this paper is to compare the simulation results in certain functionalities of Network on Chip. It’s a wide area of research on routing and topological structure. The archi-tecture of NoC is scalable network architecture. Point to point interconnection of links, switch functionality is used, verity in routing algorithms, topologies provide enhance performance as per efficiency, throughput, Latency, channel allocation manner, and comparison with the previ-ous methodology of the chip. This paper focuses on the fault tolerance adaptive routing on HPC mesh and compares its results with already implemented 2D mesh topology with parame-ters like path diversity, Total Power Consumed, Latency, Throughput, and Fault Tolerance.

Keywords:

Networks, Interconnection, Network on Chip (NoC), Efficiency, Throughput, Latency, Channel Allocation.

DOI: https://doi.org/10.32010/26166127.2020.3.1.94.118

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