Volume 3 (1), June 2020, Pages 94-118

Pankaj Dadheech, Ankit Kumar

Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur, Rajasthan, India, This email address is being protected from spambots. You need JavaScript enabled to view it., This email address is being protected from spambots. You need JavaScript enabled to view it.


Interconnection of networks use in multiprocessors multi-computer and distributed shared memory architecture; basically, it connects many networks simultaneously in each time interval. The objective of this paper is to compare the simulation results in certain functionalities of Network on Chip. It’s a wide area of research on routing and topological structure. The archi-tecture of NoC is scalable network architecture. Point to point interconnection of links, switch functionality is used, verity in routing algorithms, topologies provide enhance performance as per efficiency, throughput, Latency, channel allocation manner, and comparison with the previ-ous methodology of the chip. This paper focuses on the fault tolerance adaptive routing on HPC mesh and compares its results with already implemented 2D mesh topology with parame-ters like path diversity, Total Power Consumed, Latency, Throughput, and Fault Tolerance.


Networks, Interconnection, Network on Chip (NoC), Efficiency, Throughput, Latency, Channel Allocation.

DOI: https://doi.org/10.32010/26166127.2020.




Benini, L., De Micheli, G., & Ye, T. T. (2006). Networks on chips (Vol. 1). Burlington: Morgan Kaufmann.

Bjerregaard, T., & Mahadevan, S. (2006). A survey of research and practices of network-on-chip. ACM Computing Surveys (CSUR), 38(1), 1-es.

Bogdan, P., Dumitraş, T., & Marculescu, R. (2007). Stochastic communication: A new paradigm for fault-tolerant networks-on-chip. VLSI design, 2007.

Bouguettaya, A., Kimour, M. T., & Toumi, S. (2014, January). A New Clustering Based Routing Algorithm for NoC. In The Proceedings of the International Conference on Machine Learning, Electrical and Mechanical Engineering (pp. 9-13).

Camacho, J., & Flich, J. (2011, October). HPC-mesh: A homogeneous parallel concentrated mesh for fault-tolerance and energy savings. In 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems (pp. 69-80). IEEE.

Chen, C. L., & Chiu, G. M. (2001). A fault-tolerant routing scheme for meshes with nonconvex faults. IEEE Transactions on Parallel and Distributed Systems, 12(5), 467-475.

Chen, C., Lu, Y., & Cotofana, S. D. (2012, May). A novel flit serialization strategy to utilize partially faulty links in networks-on-chip. In 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip (pp. 124-131). IEEE.

Dadheech, P., Goyal, D., Srivastava, S., & Kumar, A. (2018). A scalable data processing using Hadoop & MapReduce for big data. J. Adv. Res. Dyn. Control. Syst, 10, 2099-2109.

Dadheech, P., Kumar, A., Choudhary, C., et al. (2019). An enhanced 4-way technique using cookies for robust authentication process in wireless network. Journal of Statistics and Management Systems, 22(4), 773-782.

Dally, W. J. (1991). Express cubes: Improving the performance ofk-ary n-cube interconnection networks. IEEE Transactions on Computers, 40(9), 1016-1023.

Dally, W. J., & Seitz, C. L. (1988). Deadlock-free message routing in multiprocessor interconnection networks. IEEE Transactions on Computers, 36(5), 547-553.

Dally, W. J., & Towles, B. P. (2004). Principles and practices of interconnection networks. Elsevier. Morgan Kauffman.

Daneshtalab, M. (2011). Exploring Adaptive Implementation of On-Chip Networks.

de Melo, D. R., Zeferino, C. A., Dilillo, L., & Bezerra, E. A. (2019, March). Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. In 2019 IEEE Latin American Test Symposium (LATS) (pp. 1-6). IEEE.

Duato, J., Yalamanchili, S., & Ni, L. (2003). Interconnection networks. Morgan Kaufmann.

El-Moursy, M. A., & Ismail, M. (2009, May). High throughput architecture for high performance NoC. In 2009 IEEE International Symposium on Circuits and Systems (pp. 2241-2244). IEEE.

Frantz, A. P., Kastensmidt, F. L., Carro, L., & Cota, E. (2006, October). Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk. In 2006 IEEE International Test Conference (pp. 1-9). IEEE

Grecu, C., Ivanov, A., Saleh, R., & Pande, P. P. (2006, October). NoC interconnect yield improvement using crosspoint redundancy. In 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 457-465). IEEE.

Harbin, J., & Indrusiak, L. S. (2013, July). Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chip. In 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) (pp. 172-179). IEEE.

Hou, J., Han, Q., & Radetzki, M. (2019, October). A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. In 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (pp. 164-171). IEEE.

Joshi, A., Batten, C., Stojanović, V., & Asanović, K. (2008, September). Building manycore processor-to-DRAM networks using monolithic silicon photonics. In High Performance Embedded Computing (HPEC) Workshop.

Kumar, A., & Sinha, M. (2014, March). Overview on vehicular ad hoc network and its security issues. In 2014 International conference on computing for sustainable global development (INDIACom) (pp. 792-797). IEEE.

Kumar, A., & Sinha, M. (2019). Design and development of new framework for detection and mitigation of wormhole and black hole attacks in VANET. Journal of Statistics and Management Systems, 22(4), 753-761.

Kumar, A., Dadheech, P., Kumari, R., & Singh, V. (2019). An enhanced energy efficient routing protocol for VANET using special cross over in genetic algorithm. Journal of Statistics and Management Systems, 22(7), 1349-1364.

Kumar, A., Dadheech, P., Singh, V., Poonia, R. C., & Raja, L. (2019). An improved quantum key distribution protocol for verification. Journal of Discrete Mathematical Sciences and Cryptography, 22(4), 491-498.

Kumar, A., Dadheech, P., Singh, V., Raja, L., & Poonia, R. C. (2019). An enhanced quantum key distribution protocol for security authentication. Journal of Discrete Mathematical Sciences and Cryptography, 22(4), 499-507.

Kumar, A., Goyal, D., & Dadheech, P. (2018). A novel framework for performance optimization of routing protocol in VANET network. J. Adv. Res. Dyn. Control. Syst, 10, 2110-2121.

Lehtonen, T., Liljeberg, P., & Plosila, J. (2007). Online reconfigurable self-timed links for fault tolerant NoC. VLSI design, 2007.

Lehtonen, T., Wolpert, D., Liljeberg, P., Plosila, J., & Ampadu, P. (2009). Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(4), 527-540.

Lit, A., Sahari, S. K., Spawi, R., et al. (2013). Power Optimization for Mesh Network-on-Chip Architecture: Multilevel Network Partitioning Approach. Proceedings of the 6th International Engineering Conference (ENCON 2013)

Manna, K., & Mathew, J. (2020). Alternative Approaches. In Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures (pp. 13-31). Springer, Cham.

Melo, D. R., Zeferino, C. A., Dilillo, L., & Bezerra, E. A. (2019). Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design. Sensors, 19(24), 5416.

Radetzki, M., Feng, C., Zhao, X., & Jantsch, A. (2013). Methods for fault tolerance in networks-on-chip. ACM Computing Surveys (CSUR), 46(1), 1-38.

Sharma, A., Tailor, M., Bhargava, L., & Gaur, M. S. (2018, June). 3D LBDR: Logic-Based Distributed Routing for 3D NoC. In International Symposium on VLSI Design and Test (pp. 473-482). Springer, Singapore.

Villanueva, J. C. (2012). High Performance and Power Efficient On-Chip Network Designs through Multiple Injection Ports (Doctoral dissertation, Universitat Politècnica de València).

Wilson, L. (2010, November). Managing Vendor Relations: A Case Study of Two HPC Network Issues. In the 24th Large Installation System Administration Conference, San Jose California

Yu, Q., & Ampadu, P. (2011). Dual-layer adaptive error control for network-on-chip links. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(7), 1304-1317.